The present invention relates to a semiconductor device that tests memories. A BIST (Built-in Self Test) is a technique which makes it easier to carry out tests on a semiconductor device by allowing the semiconductor device to test itself. A memory BIST circuit, used for testing a memory, comprises address data generator, a control circuit and an expected value comparator. Upon normal operation, data is inputted to the memory from a combination circuit on the input side, and the data, outputted from the memory, is directed to a combination circuit on the output side. At the time of a memory BIST process, the memory BIST circuit is activated and access is made to the memory by using an address-data generator so that data, outputted from the memory, is inputted to the expected value comparator. At the time of a scanning test, a scanning-use test pattern, outputted from a control-use flip-flop, is supplied to the combination circuit on the output side. Moreover, the scanning-use test pattern is used to control a selection circuit so that the combination circuit and the memory BIST circuit on the input side are switched, and connected to an observing-use flip-flop; thus, failures in the respective circuits are observed.
In the memory BIST process, the memory is generally tested by using an operational frequency. In recent years, the operational frequency becomes higher in response to higher performances of the semiconductor, and it becomes difficult to carry out expected value comparison of the output data of the memory in one cycle. For this reason, in order to achieve high-speed operations, a method in which the expected value comparing process, carried out based upon output data from the memory, is finely divided so that the respective processes are carried out in parallel with each other, (i.e. pipeline method) tends to be used.
In the pipeline system, a flip-flop is added, which forms a path from a memory to the memory BIST circuit into pipelines. However, in the case of many memories, or in the case of a great number of output bits, the number of pipeline-use flip-flops increases, resulting in an extreme increase in required area.